1. Field of Disclosure
The present disclosure of invention relates generally to the manufacture of trench-isolated semiconductor devices such as DRAM cells which may be provided in a memory integrated circuit.
The disclosure relates more specifically to certain manufacturing steps by which a juncture between trench isolation and active semiconductor may be prevented from grooving due to an isotropic etch process.
2. Description of Related Art
So-called shallow trench isolation (STI) has come into common usage for providing electrical isolation between transistors and/or other active devices of a monolithically integrated circuit. STI is particularly useful in situations where low current leakage is important such as in the fabrication of dynamic random access memory (DRAM) devices.
The basic STI process often starts with a monocrystalline semiconductor wafer (e.g., silicon). Pad oxide and silicon nitride layers are usually formed on top of the starting wafer in the recited order. These sacrificial layers will later be used for chemical mechanical planarization (CMP). After the silicon nitride has been deposited, the wafer is masked and selectively etched to form substantially vertical trenches in places where isolation oxide is to be formed. Some sidewall tapering and corner rounding may be provided. Typically, a thin layer of so-called, liner oxide is thermally grown along the interior surfaces of the trenches before a less dense form of oxide is deposited by CVD (chemical vapor deposition) to fill the bulk volumes of the trenches. Those skilled in the art understand that certain forms of silicon dioxide, namely those which are thermally grown from a monocrystalline starting substrate, tend to have relatively high density and excellent insulation characteristics. On the other hand, CVD-deposited oxides tend to be less dense and to have comparably poorer insulation characteristics. However, the CVD-deposited oxides can be formed more quickly and at lower cost, and they usually do not stress the crystal lattice structures of adjacent semiconductor material as much as would an equal volume of thermally-grown oxide. Thus, there are advantages to filling the bulk of the isolation trenches with CVD oxide.
There are different kinds of CVD oxide, including but not limited to: AP-CVD (ozone/TEOS), LP-CVD TEOS, SA-CVD, and HDP-CVD (High Density Plasma). These techniques may be used with the present invention, although not necessarily with equivalent results for each. HDP-CVD may often be used to form a more dense type of CVD oxide than the other kinds of CVD processes and it is therefore used extensively in industry.
After the CVD-based trench fill operation has been completed, the basic STI method typically continues with the provision of CMP for planarization of the wafer. The earlier formed silicon nitride often serves as a selective stop layer for the CMP process. A first wet etch (e.g., with hydrofluoric acid (HF)) is then applied to remove both of the silicon nitride layer and the underlying pad oxide layer and to thereby expose the semiconductor substrate material beneath them. A sacrificial oxide layer is then thermally grown on the exposed silicon. The thermal process creates regions of annealed crystal beneath the sacrificial oxide. Later, these annealed crystal regions will be used to form critical parts of the active devices of the monolithically integrated circuit that is being fabricated, such as the source, drain, channel, and gate oxide regions of subsequently fabricated metal oxide semiconductor field effect transistors (MOSFETs). The positioning and contouring of each of the annealed crystal regions relative to its surrounding trench oxide (planarized by CMP) will often determine how well a later-formed, gate electrode contours relative to the planarized tops and sidewalls of the trench oxide.
Those skilled in the art can appreciate that both the integrity of the trench oxide sidewalls and the quality, the vertical positioning, and the contouring of the annealed crystal region relative to the trench oxide can later play crucial roles in determining how the active devices of the wafer later behave and how much power they dissipate in different states. Prior to forming the gates, the sacrificial oxide layer that has formed above the annealed crystal region must be removed. Removal is not a trivial problem. Different kinds of oxide respond to different kinds of oxide etch processes in different ways. More specifically, the less dense oxide (e.g., HDP-CVD oxide) which often fills the bulk of the trench tends to etch more quickly than does the thermally-grown, and thus denser, sacrificial oxide. The differential in etch rates can produce undesired surface contours, including a problematic isolation-corner groove or crevice as shall be detailed below. Reliable and uniform methods are needed for reducing the undesirable effects of such differentials in etch rates which can cause grooving and associated problems.